The semiconductor industry requires economical fabrication of semiconductor circuits. Certain semiconductors, such as field effect transistors (FETs), and in particular Group III-V compound semiconductor FETs, are complex structures that are costly to fabricate. Of particular concern in the fabrication of such devices is the quality and uniformity of the devices which must perform to certain standards and characteristics. For example, high quality gallium arsenide metal semiconductor field effect transistors (GaAs MESFETs) are difficult to fabricate on epitaxially-grown layers for large scale integration. Control of device characteristics, such as the threshold voltage (V.sub.th), is difficult to achieve.
Various methods have been employed to reduce variability in the transistor fabrication process. For example, one prior art method selectively etches Group III-V compound semiconductor wafers terminating the etch at an etch stop layer located at a desired depth. Such methods essentially eliminate variability in the transistor manufacturing process. However, such methods require that the incoming epitaxial material be precisely grown to required specifications since there is no means to vary the etching depth to compensate for material deviation from the required specifications. Thus, it is desirable to monitor certain electrical characteristics of the as-grown wafers to avoid processing material that is out of specification. A useful characteristic in evaluating incoming material is to determine the threshold voltage for the active layer grown on the wafer.
Various prior art methods have been used to monitor the characteristics of epitaxially-grown semiconductor layers. Such prior art methods are cumbersome and require the use of special test samples. The test samples may not be representative of the actual epitaxial structures since they are prepared without heavily doped cap layers, an important component of the FET. For example, a commonly used prior art method, the Hall measurement, only measures the sheet resistance of the top layer as a whole. It is not informative, especially if the sheet resistance is dominated by a doped layer that will be removed during fabrication of the transistor. Thus, this method requires a test sample with an undoped cap layer. Furthermore, the test is destructive; since it requires breaking the wafer being tested. A nondestructive method for testing the actual wafers and materials to be used in the fabrication of high-frequency transistors and other circuits prior to performing significant fabrication steps, is needed.